1. Field of the Invention
The present invention is in the field of power converters. The present invention is further in the field of semiconductor switching power converters. The present invention further relates to the field of integrated hysteretic control methods for switching power converters and circuits. The present invention is further in the field of integrated switching power converters. The present invention is further in the field of frequency synchronization methods for hysteretic switching power converters. The implementation is not limited to a specific technology, and applies to either the invention as an individual component or to inclusion of the present invention within larger systems which may be combined into larger integrated circuits.
2. Brief Description of Related Art
Modern electronic applications require power management devices that supply power to integrated circuits or more generally to complex loads. In general, power switching converters are becoming more and more important for their compact size, cost and efficiency. Switching power converters comprise isolated and non isolated topologies. The galvanic isolation is generally provided by the utilization of transformers. Although the subject invention is mainly focused on non isolated switching power converters, it refers both to isolated and non isolated power converters.
Modern switching power converters are in general divided in step down power converters, also commonly known as “buck converters”, and step up power converters commonly known as “boost converters”. This definition stems from the ability of the converter to generate regulated output voltages that are lower or higher than the input voltage regardless of the load applied.
One class of modern switching power converters implemented in integrated circuits is the one comprising hysteretic control or pseudo-hysteretic control where a synthetic ripple signal is generated in a feedback network and compared to a reference to determine the duty cycle of the switching period to regulate the output voltage at the desired level. These hysteretic power converters do not include an error amplifier, a specific compensation network or a periodic signal to determine the switching frequency.
In fact their switching frequency is determined by several factors like the input voltage, the output voltage, the load, the output capacitor value, the inductor value, the hysteresis value, and the general propagation delays of the feedback network, of the comparator, of the driver, and of the output stage. Therefore, if left uncontrolled, the switching frequency of these power converters varies depending on the conditions of the converter.
However typically it is desirable to have constant switching frequency in continuous conduction mode for several reasons, but mainly to contain the harmonic content of the switching and eventually to allow the filtering of electro-magnetic interference generated by the fast slew rate of the output nodes of the converter.
Although the imposition of a constant switching frequency somewhat alters the frequency response of the power converters and complicates the analysis and study of the stability of the regulator in presence of line and load transients, the switching frequency is generally regulated and maintained constant by means of Phase Lock Loop (PLL), Frequency Lock Loop (FLL) or Delay Lock Loop (DLL) circuits. These circuits effectively modulate a loop parameter to regulate the switching frequency to be the same as the frequency of a clock signal.
FIG. 1 depicts a typical prior art block diagram of a hysteretic buck converter with switching frequency control. The oscillator 5 generates a clock signal operating at the desired frequency. The PLL block 4 compares the clock signal with the drive signal coming from the comparator and generates a voltage proportional to the error signal. The output of the PLL 4 is fed into a hysteresis control block 3 that modulates the hysteresis of the comparator 2 in order to regulate the switching frequency of the power converter to be the same as the one of the clock signal generated by the oscillator 5.
These frequency control circuits are clearly operating in closed loop and as such need to be frequency compensated to be locking as quickly as possible and be stable in all conditions. These requirements are often not trivial and the common outcome is that a PLL circuit typically requires several clock cycles to lock to a desired frequency. Furthermore these circuits are often affected by noise and present jitter or phase noise of the switching. A typical PLL requires a phase detector, a filter and a VCO (Voltage Controlled Oscillator).
In hysteretic power converters one of the most challenging transitions occurs when the load is abruptly switched on from a condition of very light load. In this case the power converter should provide a relatively stable output voltage with minimum undershoot and a fast transition from DCM (Discontinuous Conduction Mode) to CCM (Continuous Conduction Mode) where the term Discontinuous or Continuous refers to the inductor current. When the load is very low the inductor current tends to reach the zero value within the switching period, while, when the load is significant, the inductor current remains positive during the whole period.
In order to maintain high efficiency throughout all the load conditions, in DCM, the power converter needs to lower its switching frequency and to reduce, as much as possible, the current consumption of the integrated circuit. This reduction of power consumption is obtained by turning off various portions of the circuit and by slowing down (lowering the bias) the sections of the power converter that are required to continue functioning. The power converter does not need to regulate its switching frequency in DCM and it operates in PFM (Pulse Frequency Modulation), therefore the frequency synchronization circuit is either turned off or significantly de-biased.
However when the transition to CCM is required, the frequency control circuit needs to turn on and possibly to lock to the desired frequency as quickly as possible in order to avoid uncontrolled switching and high magnitude EMI generation outside of the known spectrum.
In the field of oscillators, and in particular in the field of ring oscillators, it has been proposed the use of injection locking mechanisms to reduce significantly the phase noise of the oscillators. Injection locking phenomenon is based on the observation that two oscillatory systems can lock when they have close frequencies and environmental coupling. The frequency of the two oscillatory systems is the same at the lock conditions although their phase may be different.
A very particular implementation of this mechanism has been described in the paper presented at the 35th Annual IEEE Power Electronics Specialists Conference in 2004 by Gerhard Schrom and others “A 480-MHz, Multi-Phase Interleaved Buck DC-DC Converter with Hysteretic Control”. In this paper the authors propose the injection of a synchronization signal at the reference used in a hysteretic buck power converter, and more specifically at the hysteresis generation node so that the switching instants can follow the envelope of the hysteresis band.
In other words, if the amplitude of the injected signal is adequate, the hysteresis levels can be altered to the point that the switching frequency of the power converter becomes the same as the one of the injected signal, provided that the switching frequency be lower than the free running frequency, defined as the frequency without any injected signal, and close enough in value.
Similarly, a paper by Kiichiro Taniguchi, Terukazu Sato, Takashi Nabeshim, and Kimihiro Nishijima “Constant Frequency Hysteretic PWM Controlled Buck Converter” published in 2009, describes a voltage mode buck power converter in which a current signal is injected between the feedback resistor and the input resistor that determine the hysteresis of a comparator. In this case the reference voltage is fed to an error amplifier whose output feeds the comparator.
However the cited prior art does not cover the general problem of synchronizing a hysteretic power converter to a desired frequency higher or lower than the free running frequency. In addition the amplitude of the injected signal is computed for certain values of Vin, but in present systems the input voltage may vary significantly. If the amplitude is not sufficiently large, the desired synchronization does not occur, while if it is too large a temporary undesired perturbation of the duty cycle may cause spikes or glitches in the output voltage.
Moreover if the desired frequency is not close enough to the free running frequency of the system, the switching frequency may lock to sub-harmonic frequencies with very unpleasant results. This phenomenon is also dependent on the amplitude of the disturbance signal injected.
It is therefore a purpose of the present invention to describe a novel method to synchronize hysteretic switching power converters in a manner that is reliable, simple, locking very quickly and with minimum jitter, while consuming little power. It is another purpose of the present invention to describe a method of synchronizing hysteretic switching power converters at frequencies either higher or lower than the free running frequency.